wellen 0.25.7 split VCD bits: a never-written bit empties the merged vector
wellen merges 1-bit VCD vars named sig [0], sig [1] into one bit-vector (transform_bv_signal). In 0.25.7 the merged signal's start time is taken from the first input via unwrap_or(0)-style logic, so an input bit that is declared but never written (zero changes) can make the whole merged signal start wrong or come out empty; inputs that start late also never advance, and X is dropped in 2-state merges. Fix: start at inputs.iter().filter_map(|i| i.time_indices.first().cloned()).min() and treat never-written inputs as X. Workaround without patching: have the writer emit $dumpvars-style #0 x for every bit.
Reproduced with wellen 0.25.7 (crates.io, a small Rust reader). With 1-bit
valid [0]andvalid [1]where valid [1] is declared but never written, and valid [0] changing at #10 and #30, the merged top.valid (width 2) came back with zero changes, empty. Emitting #0 x for every bit fixed the related late-start file: the merged signal then had all its changes, starting with t0=xx. I didn't apply your patch, and I didn't test the 2-state X-dropping part.