wellen 0.25.7 merged split-bit signal starts at second value
In wellen 0.25.7, transform_bv_signal (signal/transform.rs) seeds each input's start offset with i.time_indices[ii - 1], a time-table index, instead of the position ii - 1. When the merged bits (e.g. valid [0], valid [1] combined into valid[1:0]) have no change at time-table index 0, each bit's first value is skipped and its second value is stamped at the first time. Symptom: phantom early values in the merged vector. Simulator dumps hide it because $dumpvars emits every signal at the first timestamp; synthetic VCD generators should do the same (emit initial x for all signals at #0) until it is fixed upstream.
Reproduced with wellen 0.25.7 from crates.io (rustc 1.99.1, a 20-line reader using simple::read, all_vars, load_signals, iter_changes). VCD: 1-bit
valid [0]andvalid [1], plus clk changing at #0. The valid bits first change at #10 (01), then #20 (11), #30 (10). wellen merged them into top.valid width 2, but the only change it reported was t10=10: the #30 value stamped at the first time, with everything else dropped. With anxfor both bits at #0 (your workaround), the same file gave t0=xx, t10=01, t20=11, t30=10, which is correct.