Waveform output and cycle-limit knobs for common open-source RISC-V RTL sims (Ibex, CVA6, Chipyard, LiteX, BlackParrot, OpenTitan, picorv32)

Read from each repo's Makefiles/core files (late 2026 refs). Ibex simple_system and OpenTitan chip_sim_tb share lowRISC verilator_sim_ctrl: --trace=FILE (must use = form) and -c/--term-after-cycles=N; both default to FST because the .core passes --trace-fst plus -DVM_TRACE_FMT_FST in CFLAGS. Delete both from the .core to get VCD. CVA6 testharness: build with make verilate TRACE_FAST=1 (VCD; TRACE_COMPACT=1 gives FST), then run work-ver/Variane_testharness -v out.vcd +max-cycles=N prog.elf. It links libfesvr/libriscv/libyaml-cpp from the core-v-verif Spike, so that submodule plus verif/regress/install-spike.sh is required. CVA6 still pins Verilator 5.008 plus a patch. Chipyard Verilator: make debug (USE_FST=0 gives VCD), sim flags +vcdfile=PATH +max-cycles=N +loadmem=ELF (loadmem skips the slow TSI load). LiteX litex_sim: --trace always writes build/sim/gateware/sim.vcd (no path option). --trace-end is in ps (sim clock is 1 MHz, so 1 cycle = 1e6 ps) and only stops dumping, not the sim, so wrap the run in timeout. BlackParrot mk/Makefile.verilator: TRACE=1 gives FST via bsg_nonsynth_waveform_tracer and +bsg_trace=FILE; for VCD, change --trace-fst to --trace and drop the TRACER_FST define. MAX_CYCLE_P is a compile-time -pvalue, and the build dir is keyed on CFG only, so clean before changing it. picorv32 testbench.v hardcodes testbench.vcd and repeat(1000000), so sed-patch both. With GCC 15 / binutils 2.4x, bare -march=rv32imc fails on csrr/rdcycle: add _zicsr (and _zicntr for rdcycle).