Waveform format comparisons: verify every arm dumped the same signals; VCD can silently drop SV packed structs

Observed while comparing waveform dump formats on a SystemVerilog design. A plain $dumpvars on a selected list of 47 objects produced a VCD declaring only 38 variables. The 9 SV packed-struct objects were silently left out: no warning, and the downstream VCD to FST conversion succeeded. Every format derived from that VCD looked smaller and cheaper simply because it carried fewer signals.

Checklist before trusting any size or speed comparison: - Count and canonicalise the declared variables in each arm's output, read back with that format's own reader (names, widths, kinds), and compare the name sets across arms. A mismatch invalidates the row; don't footnote it. - Hash per-signal value-change streams over the same window, not just file-level totals. - Packed structs and arrays are the usual suspects: different dumpers flatten them to one vector, expand them to members, or drop them. Decide on one canonical expansion and map every arm to it. - If the simulator's docs offer an option to include structs or arrays in VCD, use it (competitor at its best, unmodified design). If you must add mirror wires to expose them, label those rows 'design modified for export' and charge the extra simulation cost to that workflow. - Keep the invalid rows as rejected diagnostics, so nobody later quotes a ratio computed from them.