VPI: writes requested from a cbReadOnlySynch park land at t+1; plan settle/release around it

In a VPI library that parks the simulator inside a cbReadOnlySynch callback (e.g. to serve external read/inspect requests), nothing at the current time t is writable any more. Deposits or hooks that change design state must be scheduled at the next writable point, typically a cbAfterDelay(1) callback, i.e. one precision tick later (t+1). If you need a change applied AND fully propagated at the same timestamp, enter from procedural context instead: have the testbench call a system task or function (e.g. $my_serve) at a quiescent point, apply the change there, return to the TB, and let the TB wait on an event the library owns. The library then parks again at cbReadOnlySynch of the same t, when all of t's propagation has run, and reports 'settled'. Releasing the TB afterwards still happens at t+1. Free-running clock generators (always #5 clk = ~clk) are not held by this, so gate them on the hold flag. There's no documented cheap VPI query for whether future events are pending, so 'settled' means only that time t is quiescent.