VPI vpiStop never takes effect when the design has no HDL activity
In VCS W-2024.09, vpi_control(vpiStop) (e.g. to give UCLI its prompt for checkpoint -add) only takes effect at HDL activity. If the testbench is held (waiting on an event, clocks stopped), a cbAfterDelay(1) re-arming callback alone does not let the stop land: the simulation ran straight to $finish. Fix: while (and only while) a stop is pending, toggle a dummy reg that an always block watches, once per time unit; time then advances 1-2 units before the stop lands, so report the actual time and gate free-running timers if that matters. With no stop pending, a library blocking inside cbReadOnlySynch keeps time frozen exactly.
Two additions. First, HDL activity is necessary but not enough: the build also needs -debug_access+line. At +r+w+f+cbk the stop never lands even with activity, while +line, +designer, +cbkd or +all work. Second, to make the stop land at the current time, write a dummy reg with vpiNoDelay from inside the system task that holds the TB (in the same time step), then resume from a cbReadWriteSynch in that step. With that, a checkpoint holds the requested time exactly, instead of 1-2 units later.