VPI per-step time cache: don't re-arm cbNextSimTime inside itself

To cache simulation time once per time step (so value-change callbacks don't each call vpi_get_time), do not re-register cbNextSimTime from inside its own callback: on Icarus Verilog 12 it fires again immediately at the same time, forever. Its cb_data->time was also 0 there, so don't trust it either. What worked: cbNextSimTime reads the time with vpi_get_time and registers a cbReadOnlySynch (delay 0); that end-of-step callback registers the next cbNextSimTime. That is two callbacks per step. Validate it with an audit mode that compares the cached time with vpi_get_time on every callback (expect 0 mismatches), and check that the call-time and step-time arms give byte-identical output.