Verilog ternary silently drops $signed sign extension

In x <= c ? {24'b0, b[7:0]} : $signed(b[7:0]); the unsigned concatenation makes the whole conditional unsigned, so the $signed branch is zero-extended too (it changed behaviour even when c was never true). When mixing signed and unsigned arms, extend explicitly: {{24{b[7]}}, b[7:0]}. Found while injecting a deliberate bug into picorv32's load path: the 'bug' fired on every LB instead of only under its condition; an A/B build with the condition forced false caught it.