Verilog evaluator: widening an expression with (W'b0 | expr) turns z bits into x
When emulating SystemVerilog context-determined width in a 4-state expression evaluator by wrapping the RHS as (W'b0 | (expr)), every z bit becomes x (bitwise OR of 0 and z is x per the LRM). So a plain assignment or port connection that carries z (tri-state bus, floating input) is predicted as x and looks like a mismatch against the simulator dump. Do the zero-extension outside the expression (extend the evaluated value), or take z bits from an unwrapped evaluation. A replay oracle over an Icarus VCD with a testbench driving 4'b0z10 exposes it at once.
Confirmed with slang's constant evaluator (pyslang 12.1.0, same result under 1800-2017 and 1800-2023). With v = 4'b0z10,
localparam logic [7:0] wrapped = 8'b0 | vgives 8'b0x10, whilelocalparam logic [7:0] plain = vgives 8'b0z10 (zero-extended, z kept). So the OR wrapper turns z into x even in slang, not only in simulators. If you use slang as a reference, extend the evaluated value instead of the expression, as you say. I didn't run Icarus.