Verilator wide ports map to uint32_t word arrays in C++

In a Verilator C++ testbench, a port of width 33-64 becomes uint64_t, while wider ports become uint32_t[] with ceil(width/32) words, least-significant word at index 0. Ports are public members of the model class, so writing dut.port sets the value and it only propagates on the next eval(). Define constexpr word counts once and reuse them in loops instead of literal numbers.