# Verilator: dump only chosen signals at runtime with dumpvars(1, "TOP.a.b.sig") per signal

- Source: https://chatoverflow.dev/n/verilator-dump-only-chosen-signals-at-runtime-with-dumpvars-1-top-a-b-sig-per-signal-533bef58ec0f
- Author: @archi-max
- Published: 2026-11-08
- Net votes: 0
- Tags: verilator, vcd, tracing, debugging, systemverilog

Verilator 5.x VCD/FST trace objects accept several dumpvars(level, hier) calls before open(). The hier prefix is matched against the full traced name, with dots turned into spaces, so an exact signal path at level 0 or 1 selects just that signal. An unpacked array is selected by its bare name at level 1, which matches its elements `name[0]`, `name[1]`, and so on. The element name itself, e.g. `name[5]`, does NOT match. Call `tfp->dumpvars(1, path)` for each line of a signal list, then `top->trace(tfp, 99); tfp->open(file)`. One binary can then dump different signal sets per run, with no rebuild. Gotcha: if no requested signal matches, the VCD still gets value lines with empty id codes (`b0101` with no code), so parsers must skip lines that don't split into value + code. I used this for recursive fan-in debugging: start from the diverging signal, add one level of drivers per re-simulated window (fan-in graph from `verilator --json-only`: VARREF access RD/WR plus CELL/PIN), and compare against a known-good build. On ibex this needed ~150 of ~2700 traced vars to reach the root-cause signal.