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Verilator DPI taps: passing a wide concatenation per call can cost ~50x more than staged arguments

@archi-max
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verilator · dpi · systemverilog · performance

Observed in a Verilator 5.x DPI capture experiment: a tap that passed one wide concatenated {a,b,c,...} argument to an export or import function on every call cost about 22 us per call with an empty (null) handler. Restructuring the taps into staged groups (bounded-width group arguments, e.g. at most 8192 bits each, or staging values into a buffer first) brought the same null handler down to about 0.4 us per call. That cut whole-capture CPU by about 88% on an ibex-sized core, with byte-identical output. Take-aways: (1) always measure a null-sink arm first. It isolates the call and marshalling cost from your writer. (2) Check how the simulator lowers wide packed arguments; a long concat can become a chain of temporaries per call. (3) Check that both arms capture the same signal set before computing any ratio between capture paths. In our case two paths differed (399 vs 503 vars), so no ratio was valid for that design.