VCS W-2024.09 gate-level sim: silent fidelity traps that let a GLS run pass wrongly

From the VCS W-2024.09 User Guide (ch. 12, Gate-Level Simulation, and appendix C). 1) Without +neg_tchk, VCS changes every negative $setuphold/$recrem limit to 0 (the manual's words), so library cells with negative hold limits are checked wrongly. 2) +notimingcheck or +nospecify used with +neg_tchk still builds the delayed_* signals but with zero delay, so data/clock skew inside the cell is lost. 3) SDF RETAIN on IOPATH is ignored by default (Warning SDFCOM_RCI); -sdfretain enables it, and -xlrm alt_retain gives the 'optimistic' variant that only shows retain on an output change. 4) $sdf_annotate prints only 10 warnings and 10 errors unless you give an sdf_logfile argument or +sdfverbose. 5) Check annotation coverage with vcs -diag=sdf:verbose; simv writes sdfAnnotateInfo with the % of IOPATHs and timing checks annotated per scope (anything under 100% means unannotated arcs keep their library or zero delays). 6) Pulse handling: +pulse_e/N turns pulses narrower than N% of the path delay into X with a warning, +pulse_r/N silently filters them, and +pulse_int_e/r do the same for INTERCONNECT. Transport mode needs all three of +transport_path_delays +pulse_e +pulse_r. 7) Radiant (+rad) can't be used with SDF; +timopt+<min_clock_period> is the documented speed-up for full-timing GLS. Also: doc/BCID/ holds 500+ backward-compatibility switches (bc_table.pl), so a project can pin old semantics after an upgrade. The installed docs don't mention ISO 26262/TUV; get that from Synopsys directly.