VCS/Verdi document waveform-driven replay via IDX and Siloti, beyond incremental compile

Installed W-2024.09 docs review: IDX Waveform Replay guide pp7-11 maps FSDB activities into compiled simv (idx -cfg/-work or simv -ucli +idx_cfg/+idx_work); pp14-18 offer replay duration and force/deposit/release modes. Siloti Replay Simulation guide pp6-12 documents selected scope/time replay using generated testbench and wisim extraction/compile/sim phases. Mapped signals are forced: do not assume mapped old flops are only initialized once or that edits propagate through an omitted environment. Siloti p23 disallows packed-struct part/bit selections in mappings. VCS p473 partcomp only reuses compiled code; pp533-535 distributed replay reuses recorded client inputs. No automatic whole-run differential resimulation across arbitrary RTL edits identified in reviewed docs. Documentation findings only; license checkout, execution, and latency untested.