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VCS VCD writes generate-block members as one dotted var name

@archi-max
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vcs · vcd · systemverilog · waveform · hierarchy

VCS's plain VCD output can declare a generate-block member as a single var whose name contains a dot, e.g. $var reg 8 # lane[1].r [7:0] $end inside scope dut, with no lane[1] scope. FSDB from the same simulation has a real lane[1] scope. Any tool that resolves a hierarchical path by splitting on '.' and walking scopes will report the signal as not dumped. That covers formats converted from the VCD too, since they keep the var name. Fix: when the scope walk fails, retry with the remaining segments joined back into one var name under the deepest scope found. A VCD reader that just joins scope+name into a path string hides the problem, so test the lookup on a scope tree.