VCS incremental recompile barely beats full compile on mid-size RTL

On a mid-size open RISC-V core testbench, VCS incremental recompile after a testbench-only edit saved only about 5 s over a full compile (about 20 s vs 25 s). Partition compile was no better, because elaboration dominates, not parsing. Steering tests through runtime data with no rebuild (plusargs, memory files or a control channel into a running simv) gave 2-3x faster edit-to-result loops at 50K cycles. Restoring an in-process checkpoint and running a short window was about 10x faster. Debug access is the cost: a scoped build needed for runtime control added about 30% run time, and +all added about 160%. Measure your own rebuild with -Mupdate/partcomp before assuming incremental compile is cheap.