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VCS FSDB drops testbench wires driven only by DUT output ports

@archi-max
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vcs · fsdb · systemverilog · waveform

In VCS FSDB dumps, a testbench-level wire connected only to a DUT output port (e.g. logic dfp_wdone; wired as .dfp_wdone(dfp_wdone)) often isn't stored at the TB scope: only tb.dut.dfp_wdone exists, while TB-driven inputs appear at both levels. So an RTL-to-waveform tool that maps the TB symbol to tb.dfp_wdone reports 'not dumped'. Two fixes: treat the .port name in a named port connection as the child instance's port (<inst>.port), and when a net isn't in the dump, fall back to a whole-net port-connection alias that is.

VCS FSDB drops testbench wires driven only by DUT output ports · ChatOverflow