VCS bug: &{N{s}} / |{N{s}} on a 1-bit z returns z instead of x (repro, versions, flags)

Synopsys VCS treats a reduction over a replicated 1-bit signal as the signal itself, so a z goes straight through. IEEE 1800 says z behaves like x in AND/OR (the bitwise and reduction tables), so a reduction can only give 0, 1 or x, never z. Icarus 12.0 and slang 12.1 both give x.

Minimal repro (one file, one statement):

module m;
  logic s2 = 1'bz;
  initial begin #1; $display("%b", & {1{s2}}); end
endmodule

vcs -full64 -sverilog t.sv -o simv && ./simv prints z on R-2020.12-SP1-1, U-2023.03-SP2, U-2023.03-SP2-2-T and W-2024.09, with default flags. O-2018.09-SP2-3 (VCS-MX) prints x.

The same family with & {2{s2}}, & {3{s2}}, | {2{s2}} or & {s2,s2}: - with default flags, x when alone (correct), but z when the module has enough other uses of s2 (see the companion post on context dependence); - z on every version in a one-statement file with -debug_access+all (also +pp and -debug_acc+all) or +rad; & {s2,s2} only under +rad; - (& {2{s2}}) === 1'bz prints 1 in the bad configuration, so the stored value really is z, not a $display formatting artifact.

Not affected in any configuration: & s2, s2 & s2, ^ {2{s2}}, ~& {2{s2}}, and & r2 with r2 = 2'bzz (except +rad in a multi-statement file). That pattern fits a 2-state rewrite, &{N{a}} -> a, which is valid in 2-state and for x but wrong for z.

Checked and ruled out: a time-0 race (the only assignment is the declaration initializer, read after #1; moving it into initial gives the same result), output pairing (every line carries its own index), nondeterminism (identical across recompiles), and version mix-ups (simv banner matches). -xprop=tmerge/xmerge, -O0, -Xnoopt and -lca do not change it.

Workaround: don't rely on a reduction of a replication to propagate x/z in VCS. If you are using VCS as the reference in a differential test of a 4-state evaluator, treat z or 0 from these shapes as a VCS defect and re-check with Icarus or slang constant evaluation.