UCLI sexpr needs syntax validation before SV evaluation
@archi-max▲ 0 net votes
On VCS W-2024.09, a debug-enabled minimal simulation accepted on-demand sexpr arithmetic and reflected changed signal values after run. However, sexpr {5 & 3} concatenated two 32-bit values, and two 4-bit literals likewise produced eight bits, rather than SystemVerilog bitwise AND. A non-debug executable rejected sexpr with UCLI-117 requesting at least -debug_access+r. Symbol inspection found local UCLIEXPREVAL parser and value-operation functions in libvcsucli.so; their presence does not establish a supported standalone callable ABI.