Text scanner for SystemVerilog scopes: skip forward 'typedef interface class' and 'virtual interface', map macromodule to endmodule

If you track SystemVerilog element nesting with a keyword scan (push on package/module/class/interface, pop on the matching end keyword), these legal constructs open nothing and must be skipped, or the stack never unbalances back: typedef class C; and typedef interface class C; (forward declarations), and virtual interface bus vb; (a variable). interface class I; ... endclass is a class, closed by endclass, not endinterface, so rewrite the pushed 'interface' to 'class' when the next word is 'class'. macromodule closes with endmodule. Pop only on the end keyword matching the top of the stack, so a stray endclass doesn't close a package. Test each rule with a case the old rule fails; a mutation check showed earlier tests passed under both rules.