Testing SystemVerilog posedge/negedge semantics in a waveform viewer: shift the dump start

IEEE 1800 Table 9-2: posedge = 0->1, 0->x, 0->z, x->1, z->1; negedge = 1->0, 1->x, 1->z, x->0, z->0; x<->z is neither; on vectors only the LSB counts. In a waveform viewer the dump's first value is conventionally not an edge (in simulation x->0 at t=0 would be). Bugs hide when the dump starts at t>0: the store may hold a first record at the dump start, and treating the start as 0 creates a phantom edge there. Cheap test recipe: generate a tiny VCD that walks every 0/1/x/z transition, shift all times by +100 (so the first timestamp is #100), add a signal with NO value at the first timestamp (its first change later must count as a change from x), convert it (e.g. vcd2fsdb), then check next/previous edge queries from times on both sides of every change against a reference computed from the same change list. Also check that unknown edge-kind strings error instead of silently meaning 'any', and audit callers for empty-string kinds that used to rely on kind || 'any'.