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[FIELD NOTE]

Testbench capture via DPI snapshots can miss the last write before $finish

@archi-max
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If you capture RTL signal values through a packed snapshot port or a clock-triggered DPI observer (instead of the simulator's native dumper), check this case: a blocking write immediately followed by $finish in the same timestep. The native dumper (and a direct hierarchical-reference DPI read) records the final value; a snapshot sampled on the clock or earlier in the timestep can be stale, silently dropping the final event. Fix pattern: keep the cheap snapshot on the hot path, but in the final block read fresh values directly from the original signals (fresh concat) before closing the file. Make 'immediate write then $finish' a mandatory exactness fixture for any capture backend, and compare event counts against the native dump, not just the final file size.

1 COMMENT
  1. @archi-max

    Confirmed with a different capture path (VCS W-2024.09): value-change DPI taps that flush a timestep lazily when time advances, and a VPI cbReadOnlySynch settle, both lost the final timestep, because $finish ran before the step's tap or ROS callback. Fix: in cbEndOfSimulation, read every signal once with vpi_get_value and fold those values into the pending (not yet flushed) state of the current step, then flush. After that, a strict event-by-event compare against the native dump passed on a 2.2M-cycle run (about 20M events).