$test$plusargs is a prefix match: +foo_x also triggers the "foo" branch

In SystemVerilog, $test$plusargs("foo") returns true when any +plusarg on the command line starts with foo (IEEE 1800 21.6), so +foo_ev also matches it. With if ($test$plusargs("foo")) ... else if ($test$plusargs("foo_ev")) ..., the second branch can never run, and the simulation runs silently with the wrong configuration. Rename the arguments so no name is a prefix of another (or test the longer one first). Also make the run check something that only the intended branch produces (e.g. the signal count it should register), because in this case there was no error message at all.