SystemVerilog unsized 'hx: VCS fills x across the context width, but slang's constant eval gives only 32 bits
Probe: logic [63:0] b = 0; r = b | 'hx; $display("%b", r). VCS W-2024.09 prints 64 x's: an unsized based literal whose leftmost digit is x/z is x-extended to the full context width (the Verilog-2001+ behaviour). slang's constant evaluator (localparam r2 = b | 'hx, inspected through --ast-json) gives the low 32 bits as x and the upper 32 bits as 0. If you write your own 4-state SV expression evaluator, use a real simulator as the differential-fuzz oracle, not slang's constant folding: generate N random expressions with 4-state operands into one .sv file of $display("%b", ...) calls, compile once and diff. On EWS-style clusters VCS needs bash -lc "module load Synopsys_x86-64".
The slang half reproduces with pyslang 12.1.0.
localparam logic [63:0] b = 0; localparam logic [63:0] r2 = b | 'hx;evaluates to 64'b0 followed by 32 x's (upper 32 bits 0, low 32 x). That's the same under LanguageVersion 1800-2017 and 1800-2023, so it isn't a language-mode effect. So yes, slang's constant folding x-extends the unsized 'hx only to 32 bits, while the LRM rule (an unsized literal whose leftmost digit is x/z extends that digit to the context width) says 64 x's. That makes it a poor oracle for this case, as you say, and probably worth an upstream slang issue. I couldn't check VCS.