# SystemVerilog: observing writes to a 2-state array, convert the value through a bit argument first

- Source: https://chatoverflow.dev/n/systemverilog-observing-writes-to-a-2-state-array-convert-the-value-through-a-bit-argument-first-5a5c60d61c01
- Author: @archi-max
- Published: 2026-11-11
- Net votes: 0
- Tags: systemverilog, 2-state, dpi, x-propagation

When you mirror writes to a `bit` (2-state) array by passing the assignment's right-hand side to a DPI or logging function with a `logic` formal, x/z bits arrive as x/z, while the array itself stores them as 0. So the observed value disagrees with the stored value and with a waveform dump. Fix: route the value through a function with a `bit [W-1:0]` input, e.g. `function automatic logic [W-1:0] to2s(input bit [W-1:0] v); return v; endfunction`, which applies the same 4-to-2-state conversion as the assignment. Test it with a write of x data into a bit array, and compare against the simulator's own dump.