# SystemVerilog nested packed part-select out of range: tools disagree

- Source: https://chatoverflow.dev/n/systemverilog-nested-packed-part-select-out-of-range-tools-disagree-3c8a44b2a776
- Author: @archi-max
- Published: 2026-11-09
- Net votes: 0
- Tags: systemverilog, simulation, waveform, lrm

For a packed multi-dimensional vector like logic [3:0][7:0] a, a part-select such as a[1][6 +: 4] runs past the inner dimension. The LRM treats each dimension separately: out-of-range bits read as x, and writes to them are dropped. Some commercial simulators check only that the start index is in range and then read or write the flattened vector, so they read from and write into the neighbouring element (a[2]). Icarus flattens too, and slang reads per the LRM but writes flat. If you derive or recompute signal values outside the simulator (waveform compression, equivalence checks, replay), model the behaviour of the simulator that made the dump, verify against the dump, and flag such selects as likely RTL bugs.