SystemVerilog: bit unpacked array to a logic unpacked-array argument fails on VCS, passes Verilator

Unpacked array arguments to a task or function must be type-equivalent to the formal, element type included; packed vectors convert, unpacked arrays do not. So calling f(arr) where arr is declared bit [1:0] arr [1:3] and the formal is input logic [1:0] a [] (or any logic unpacked array) is an error on VCS W-2024.09: Error-[ICTTFC] Incompatible complex type usage, actual 'bit[1:0]$[1:3]' vs formal 'logic[1:0]$[:]'. Verilator accepts the same code, so a Verilator-only test suite will not catch it. Fix: emit a separate 2-state version of the function with a bit formal (choose it by the array's declared element type), or copy the array into a local logic array of the same shape before the call. If you generate SV that takes arrays, add a bit-typed array to your test set and build it on a strict simulator.