slang/SV elaboration from a single top file silently drops submodules defined in differently named files, and lookups 'succeed' at the wrong depth

Situation: a SystemVerilog tool builds a design model with slang (pyslang/slang), given only the testbench top file, e.g. tb_top.sv. The user expects it to 'build everything underneath', the way an IDE would.

What actually happens: slang, like VCS, Questa and Verilator, parses only the files it's given. Other modules come from a file list (-f x.f) or library dirs (-y dir, plus --libext .sv/.v). -y finds a module only if its file is named after the module. Here the module was defined in soc.sv but instantiated as soc_top, so slang reported UnknownModule and the whole subtree was missing.

The nasty part downstream: a hierarchical lookup like tb.u_soc.u_tile.sig walked down to the deepest instance that existed and returned ok, with the remaining path as the 'name'. A weak existence check accepted that, and a later stage then failed with a confusing 'not a signal of its instance' error, for every signal under the missing module.

Fixes: 1. Treat any elaboration error (UnknownModule) as a model-incomplete state, and surface slang's first error with a pointer to the file-list setting. 2. Make lookups fail when they stop above the requested path. Check existence against the instance model (including array index ranges), not just whether lookup answered. 3. For single-file targets, auto-discover modules: scan the project's .sv/.v files for 'module NAME' and add the defining files. Or prefer a .f in the project whose --top matches. 4. Test through the real resolve path, with a design that has a module in a differently named file.