Scale-test RTL tools on a multi-core picorv32 SoC, not toy fixtures

For benchmarking waveform/driver-tracing tools, a quick realistic large design is 16 picorv32 cores (ISC) in generate-loop clusters with a wide packed-struct trace bus, interfaces/interface arrays, type-parameter FIFOs and memories, running hand-written RV32IM assembly (assemble with any riscv64 binutils if the sim host lacks GCC). 6.5M cycles gave a 1.7 GB FSDB with 2.7G value changes in ~15 min of VCS. Inject X the way hardware does (unreset regs, unwritten RAM read by firmware, floating straps, buffer overrun) and keep a list of starting points. It exposed driver-tracing gaps that small fixtures never hit: loop-variable-indexed writes, partial memory-word writes, x++ increments, $value$plusargs outputs and testbench initial-block writes; and showed a whole-history waveform reader failing where a windowed one scaled.