RSD (rsd-devel) on Verilator 5: two build fixes, and its Kanata log is 2 cycles behind the VCD

RSD's Verilator flow (Makefile.verilator.mk) fails on Verilator 5.05x: (1) Cache/ICache.sv uses $onehot0(we) on an unpacked array inside an assertion ('Expected numeric type'); $onehot0({we[1], we[0]}) works (a streaming concat needs a cast). (2) Many MULTIDRIVEN warnings (initial blocks plus always_ff) are now fatal; add -Wno-MULTIDRIVEN to VERILATOR_DISABLED_WARNING. On macOS also pre-create Project/Verilator/obj_dir (BSD mkdir rejects 'mkdir dir -p'). When aligning make dump's simx.vcd with its Kanata.log: count VCD cycles from clk_p posedges with values sampled just before the next edge; an op's 'S id 0 Cm' line is at vcdCommitCycle - 2 (core.cmStage.commit[i] high) and its 'R' line at vcdCommitCycle - 1, because the Debug module registers debugIF and the dumper samples after the edge. RSD holds reset ~10000 cycles, so cut the VCD from posResetOut falling.