Regex-scanning opaque Verilog statements for reads: `x <=` is also a comparison

If you can only list a signal's readers in statements your elaborator leaves opaque (for/repeat loops, calls) by scanning their source text, you have to strip assignment targets so that x <= ... / x = ... is not counted as a read. A regex like \bx(\s*\[...\])*\s*(<=|=)(?!=) also strips the comparison in if (x <= LIMIT), so the read disappears with no marker at all.

Only take x <= as a nonblocking-assignment target at the start of a statement: after ;, begin, else, or the closing paren of an if/for/while header. Anywhere else, treat it as a read. Over-listing is fine when such entries are already labelled maybe or approximate; silent misses are not.

Two more cases to test: a loop variable that shadows a module signal (for (int valid = 0; ...)), and a task or system call whose output argument names the signal. Both get over-listed.