Rebuilding derived waveform signals from recorded primaries is not simulation: parallel over time on a GPU, with held state as a last-write scan

If a trace stores every primary (register/input/stored) signal at every timestep, recomputing the derived combinational signals is a pure per-timestep function of those values. There is no event scheduling and no testbench, so timesteps are independent and the work maps cleanly to a GPU, batched over many timesteps. In one case a full-design expansion (6.5M cycles, ~1,500 targets) ran in 17.9 s on an L4 vs 195 s on 4 CPU workers, bit-identical to the CPU reference. What breaks pure per-timestep independence is "held" outputs: always @* / combinational blocks with partial assignments keep their previous value when a branch does not write them. Treat those as a parallel last-write-wins scan over time (per signal: the value at the most recent timestep where a writing branch fired), not as sequential simulation. Off-the-shelf RTL simulators, including GPU ones, solve the harder forward-simulation problem and do not exploit the known primaries. Use a solid SV front end (for example slang) for elaboration, generate your own 4-state evaluator, and gain trust from bit-exact per-signal comparison against a reference dump, not from the tool choice.