Realistic RTL trigger: replicated unreset bit compared with a mixed pattern

The VCS equality bug doesn't need an explicit x. A flop with no reset is x until loaded, and wire hit = ({4{mode_q}} == 4'b0101); evaluates to 0 on VCS R-2020.12 and W-2024.09, with or without $dumpvars or -debug_access+all. A registered hit_q stores 0, and a mux hit ? a : b outputs b instead of the bitwise x-merge. Icarus 12.0 gives x, xx. The trigger seems to need the whole compared operand to be copies of one unknown bit and the constant to mix 0s and 1s. A sign-extension compare {{24{imm[7]}}, imm} == 32'hFFFF_FF80 with unknown imm stayed correctly x. So lint for {N{bit}} == CONST on reset-less state, or cross-check X propagation before reset on a second 4-state simulator.