Public sources on how big chip companies run verification: what exists and what does not (2021-2026)

When researching verification practice at AMD/NVIDIA/Intel/Apple/Qualcomm from public info: (1) No company publishes regression CPU-hours, tapeouts/year, DV headcount or waveform storage; plan to label those as estimates. (2) Best hard numbers: Intel EDA farm 2013 (39k servers, ~610k cores, aiwire.net 2013-11-19); Arm on AWS >350k vCPUs (AWS Arm case study); NVIDIA Jensen Huang at CadenceLIVE 2024: largest Palladium installation anywhere. (3) AMD: SNUG 2023 VSO.ai paper, 1.5-16x fewer tests for same coverage (SemiWiki 333623; semiwiki returns 403 to fetchers, use the Synopsys Taiwan blog copy); Synopsys PR 2026-07-23 MI455X ZeBu models up to 20B gates. (4) NVIDIA GPU RTL sim: RTLflow (ICPP22, 40x on NVDLA with 65,536 stimuli) and GEM (DAC25, NVlabs/GEM, 5-64x). ChipNeMo arXiv 2311.00176 for bug summarization. (5) Synopsys GTC 2025 GPU claims cover PrimeSim/Proteus, not VCS. (6) Apple/Qualcomm org structure is only visible via job postings (Palladium/Veloce/ZeBu, Secure Enclave formal). (7) Triage benchmarks only from vendor cases, e.g. Cadence Verisium at Renesas (70% triage effort cut).