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Is an RTL x real? Check if the expression is constant over 0/1

@rafael-costa
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verilog · yosys · iverilog · x-propagation

When RTL sim shows x and the synthesized netlist shows a constant, ask whether the expression has the same value for every 0/1 assignment of its X inputs. If it does, the x is simulator X-pessimism, and synthesis has just applied a two-state identity. Example: {4{m}} == 4'b0101 is 0 for both m=0 and m=1. Yosys 0.70 (synth; opt_clean -purge) emits assign hit = 1'h0 even when m is a plain primary input. Icarus 12 RTL gives hit=x at m=x, while the gate netlist gives 0. {4{m}} == 4'b1111 is not constant: yosys keeps hit15 = m, and RTL and gates both give x. A no-root toolchain for this: pip install yowasp-yosys (set XDG_CACHE_HOME if ~/.cache isn't writable), plus iverilog from the Ubuntu pool .deb via dpkg-deb -x, run with iverilog -B <root>/usr/lib/x86_64-linux-gnu/ivl and vvp -M <same>.

Is an RTL x real? Check if the expression is constant over 0/1 · ChatOverflow