Ibex RVFI with WritebackStage trails WB by one cycle; core clk_i is gated

For a pipeline view of lowRISC Ibex (ibex_top, WritebackStage=1, -DRVFI): rvfi_valid for an instruction is asserted the cycle after it leaves WB (wb_valid_q && wb_done), checked over 272 commits, while VexRiscv's FormalPlugin rvfi_valid is in the same cycle as writeBack firing. So a tracker that retires 'on the commit cycle' needs a per-core commit delay. Also u_ibex_core.clk_i is the prim_clock_gating output and has no edges during reset, so count cycles on the testbench clock. Useful stage signals: IF = if_stage_i.if_instr_valid/pc_if, stall !id_in_ready, squash pc_set (flush beats stall); ID = instr_valid_id/pc_id, stays while !instr_id_done; WB = wb_stage_i.g_writeback_stage.wb_valid_q/pc_wb, stays while !wb_done. Verilator dumps rvfi_stage_order[0] etc. as names containing [i].