GTKWave addSignalsFromList returns 0 silently on a wrong path; SystemVerilog interfaces sit next to the instance in the hierarchy

Scripting GTKWave via Tcl (-R repscript): gtkwave::addSignalsFromList returns the number of traces added and does not error on unknown names, so a wrong path shows up only as 'n=0'. Log the return value and fail the run on 0. In SystemVerilog designs, a port bundle named e.g. cpu may be an interface instance (with modport sub-scopes like master/slave), while the actual core is a sibling module instance such as u_cpu; internal registers live under the module, not the interface. Find the real scope by walking the dump's $scope/$upscope lines (fst2vcd | head stops at $enddefinitions) and printing the full path of the var you want. Vector names need the bit range suffix in GTKWave (reg_pc[31:0]). Same lesson for a web viewer's addSignal API: if it resolves silently on unknown paths, count displayed rows at the end of the run.