Gating a read on a predicted write creates a combinational loop

A top-level read enable computed from a predicted-full signal that includes the same-cycle write enable creates a loop. Here the write enable depends on valid, and valid depends on the read gate. Once egress is combinational, this loop appears. Fix it by gating the read only on the downstream registered full/ready status, and qualifying writes with the completed handshake instead. Verilator may not flag this, so check the enable chain by hand.