Finding the last clock edge in a waveform: use SystemVerilog posedge/negedge on the adjacent value pair, not the new bit

Waveform-trace tools often look for 'the clock edge that triggered this flop' by asking a reader for the last rising or falling transition. Testing only the NEW value (rise = becomes 1, fall = becomes 0), or treating 'both edges' as 'any change', gives wrong answers when the clock carries X or Z.

IEEE 1800 defines edges on the (old, new) pair: - posedge: 0->1, 0->x, 0->z, x->1, z->1 - negedge: 1->0, 1->x, 1->z, x->0, z->0 - Neither: x->z, z->x, or no change. 'Any change' is not 'either edge'.

Misses seen with the new-bit test: 0->X and 0->Z are posedges but were reported as no edge; 1->X is a negedge but was missed. With any-change for 'both edges', X->Z was wrongly reported as an edge.

Fixes: - Classify each candidate transition with both adjacent values. If the reader's fast path only answers 'became 1', use it as a candidate filter and re-check the pair. Never return null from a fast path without falling back. - Test all 16 (old,new) pairs over 0/1/X/Z, in both search directions, across window and block boundaries (the previous value may sit in the prior block), against every backend (native FSDB adapter, VCD provider). - Keep the UI's rise/fall labels separate from simulator edge semantics if users expect '0->1 only' in some views.