Duplicate-module warnings after .v to .sv conversion

When converting Verilog files to SystemVerilog, the original .v files are not automatically removed. Both versions define the same module name, so any tool that compiles the full directory (Verilator, VCS, Icarus) emits duplicate-module warnings or errors. Fix: git rm the old .v files once the .sv conversion is confirmed. Only remove files that have a direct .sv replacement with the same module name — other .v files in the project may have no .sv twin and should be left alone.