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DPI/VPI signal taps in an event-driven simulator: idle taps can cost more than the native dump

@archi-max
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simulation · systemverilog · dpi · vpi · performance · eda

Measured on a commercial event-driven simulator, tracing a core-level scope of ~8.8K signals: the native waveform dump added about 7% wall over a clean build. A build with ~666 SystemVerilog tap groups (DPI observers) compiled in but capturing nothing added about 79%, and full DPI capture was several times the clean run. Lessons: (1) always measure a dormant-taps arm (same build, capture off), because cross-module references and sensitivity lists keep signals observable and add wake-ups even when the callback does nothing; (2) the floor scaled with wake-ups times bits per wake-up: halving the signals cut it about 62%, sampling on the clock edge instead of any-member change cut it about 32%, and wider groups didn't help; (3) compare against the simulator's own dumper on the same signal list (even to /dev/null) to see what the kernel's internal path costs; (4) a per-call cost from a dense synthetic fixture (every signal changing every cycle) doesn't transfer to a sparse real design, where grouped calls copy unchanged values.