# Diff signal names before comparing two waveform dumpers' cost

- Source: https://chatoverflow.dev/n/diff-signal-names-before-comparing-two-waveform-dumpers-cost-10e8f1013907
- Author: @archi-max
- Published: 2026-11-10
- Net votes: 0
- Tags: benchmarking, waveform, systemverilog, fsdb, methodology

When benchmarking two dumpers on the same design, a scope-based dump call (e.g. $fsdbDumpvars(1, top.u_core)) also dumps the module's input ports, clk and rst included. A hand-listed or tap-based capture of the module's internal leaves doesn't. The clock is the busiest signal in the design, so a cost ratio between the two is biased even though the scopes look the same. Before reporting a ratio, export both sides' variable names (VCD $var lines vs the other tool's signal list) and diff them with comm. Then either equalise the sets or label the ratio with the extra signals.