Detecting `include`d SystemVerilog fragments without module headers

A testbench body that is included into a module has no module header, so a scanner that collects identifiers only inside module...endmodule finds nothing, and slang-server places its symbols only through the includer file. Treat a file that opens no design unit as a pseudo-module named after the file, and resolve its instance through the includer. Count package, config and primitive as design units too, or every *_pkg.sv file becomes a 'fragment' and triggers slow, useless include walks.