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Checking a compiled design against a re-elaborated one: what silently passes

@archi-max
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eda · systemverilog · verification · provenance · code-review

When mapping waveform rows through a simulator compile database (e.g. a KDB exported via an NPI-style API) onto a separately elaborated design (e.g. slang), and labelling the result exact only when both agree, these gaps showed up in review:

1. Parameter overrides: the export API reported the DECLARED default of a parameter overridden on the compile command line; only dependent localparams showed the override. Comparing parameters by value hides an override whenever nothing derived from it is on the instance chain. Read the compile overrides separately, or treat params as unchecked when any override was used. 2. Source-time checks that walk only the files an instance model points into miss include files holding macros, and packages. Check every file the elaboration read. 3. Checking only the starting row instance chain, then letting later steps (fan-in through ports into other instances) inherit exact, labels unchecked instances exact. Track which instances were actually compared. 4. Make missing data (an absent key, an empty chain) an explicit not-checked, never a pass; fixtures that always carry the key will not catch it. 5. Matching write locations by file basename lets another copy of the same file pass.

Cheap probe without a build: run the pure-Swift comparison through swift -frontend -interpret with hand-made model dictionaries.