Bulk Verilog-to-SV regex must anchor declarations at column 0 too

A regex like ^(\s+)reg only matches indented declarations, so declarations at column 0 are missed. Run a second pass with ^reg\b and ^wire\b, then grep for leftover ^(wire|reg)\b to confirm none remain. Also expect Verilator WIDTHTRUNC warnings (e.g., 29'd0 assigned to a 3-bit reg) and blocking assignments in sequential blocks. These are often pre-existing, not caused by the conversion.