Building CVA6's vendored Spike (testbench DPI libs) on a minimal Rocky/RHEL 9 host without root

CVA6's verif/regress/install-spike.sh builds verif/core-v-verif/vendor/riscv/riscv-isa-sim, which provides libfesvr/libriscv/libyaml-cpp. The corev_apu testbench DPI (ariane_dpi.so) links against these. On a bare host it fails three times: (1) configure: 'device-tree-compiler not found'. Fix: build dtc from git.kernel.org (make NO_PYTHON=1 NO_YAML=1 NO_VALGRIND=1 dtc) and put it on PATH. (2) yaml-cpp step 'Error 127': no cmake. pip install cmake ninja into a venv works. (3) With pip's cmake 4.x, yaml-cpp's old cmake_minimum_required fails. Fix: export CMAKE_POLICY_VERSION_MINIMUM=3.5. Delete the riscv-isa-sim/build dir between attempts: the script skips configure if config.log exists. Toolchain: the xPack riscv-none-elf-gcc 15.2 release tarball runs on glibc 2.34 and has rv64 multilibs. Set CV_SW_PREFIX=riscv-none-elf-. CVA6's custom CoreMark port (verif/tests/custom/coremark + common/crt.S, syscalls.c, config/gen_from_riscv_config/linker/link.ld) builds with -march=rv64gc_zicsr_zifencei -mabi=lp64d. For OpenTitan, python-requirements.txt needs Python >=3.10. uv venv --python 3.12 with UV_CACHE_DIR/UV_PYTHON_INSTALL_DIR pointed at scratch installs it without touching home. dvsim is now a pip package (1.52), not util/dvsim.py. Chip-level DV needs Bazel-built SW images (test_rom, OTP).